The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device suited to form memory means having a very large capacity.
The error correction technology used in conventional semiconductor memory devices will first be explained, to facilitate the understanding of the fundamental function of a semiconductor memory device according to the present invention. A first example of the conventional error correction technology is described in the February 1981 issue of the ISSCC DIGEST OF TECHNICAL PAPERS pages 80 and 81. In this example, as shown in FIG. 10, an external address is compared, on a semiconductor chip, with a defective address written in internal programming elements to select spare memory cells. In more detail, the programming elements are constructed so that transistors Q.sub.o to Q.sub.n included in a decoder are all put in an OFF-state in response to specific external address signals X.sub.o to X.sub.n, and thus a node A is put to a high level in response to the specific external address signal X.sub.o to X.sub.n, to select spare memory cells.
A second example is a redundance method carried out for individual memory blocks on a semiconductor wafer, and is described in the IEEE, Journal of Solid State Circuits, Vol. S-15, No. 4, August 1980, pages 677 through 686.
This method employs an external controller. In a case where defects are present in one of individual memory blocks, the defective memory block is changed over to a normal memory block with the aid of the external controller. That is, external means for processing the defective memory block is required.
A third example is a redundance method proposed in Japanese patent application Post-Examination Publication Nos. 46-25,767 and 47-6,534. In this method, the address of a defective bit is stored in an associative memory, and it is ascertained that an external address coincides with the defective bit address stored in the memory, to inform a spare memory of a new address, thereby reading out a normal bit.